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mos integrated circuit pd8891 (5340 5340) pixels 3 + 2670 pixels 3 color ccd linear image sensor data sheet document no. s16039ej2v0ds00 (2nd edition) date published march 2003 ns cp (k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2002 description the pd8891 is a color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the pd8891 has 3 rows of (5340+5340) staggered pixels, and each row has a dual-sided readout type of charge transfer register, and has 3 rows of 2670 pixels, and each row has a single-sided readout type of charge transfer register. and it has reset feed-through level clamp circuits and voltage amplifiers. therefore, it is suitable for 1200 dpi/a4 color image scanners, color facsimiles and so on. features ? valid photocell : (5340+5340) pixels 3 + 2670 pixels 3 ? photocell pitch : 5.25 m (1200 dpi), 10.5 m (300 dpi) ? photocell size : 5.25 5.25 m 2 (1200 dpi), 10.5 8 m 2 (300 dpi) ? line spacing : [1200 dpi sensor] 52.5 m (10 lines) red line - green line, green line - blue line 10.5 m (2 lines) odd line ? even line (for each color) [300 dpi sensor] 42 m (4 lines) red line - green line, green line - blue line ? color filter : primary colors (red, green and blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 48 dot/mm a4 (210 297 mm) size (shorter side) : 1200 dpi us letter (8.5? 11?) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 5 mhz max. ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits :: voltage amplifiers ordering information part number package pd8891cy ccd linear image sensor 22-pin plastic dip (10.16 mm (400))
data sheet s16039ej2v0ds 2 pd8891 block diagram 22 20 1 11 7 8 16 15 5 17 tg1 (blue) tg2 (green) tg3 (red) 1l 2-1200 1-1200 2-300 1-300 14 13 2-300 1-300 gnd gnd v od v out 1 (blue) 21 v out 2 (green) 2 12 10 9 v out 3 (red) clb 19 sel photocell (blue) ccd analog shift register ccd analog shift register transfer gate transfer gate d154 d156 s10680 s2 d162 d47 d155 s10679 s1 d161 d153 d162 d161 d162 d161 d154 d156 s10680 s2 d47 d155 s10679 s1 d153 d154 d156 s10680 s2 d47 d155 s10679 s1 d153 photocell (green) ccd analog shift register ccd analog shift register transfer gate transfer gate photocell (red) ccd analog shift register ccd analog shift register transfer gate transfer gate 4 rb 3 2l photocell (blue) ccd analog shift register transfer gate d40 s2670 d13 d39 s1 s2 d41 photocell (green) ccd analog shift register transfer gate d13 d39 s1 s2 photocell (red) ccd analog shift register transfer gate d13 d39 s1 s2 d40 s2670 d41 d40 s2670 d41
data sheet s16039ej2v0ds 3 pd8891 pin configuration (top view) ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) ? pd8891cy nc no connection v out 2 output signal 2 (green) v out 1 output signal 1 (blue) 2670 2670 2670 red green blue 1 1 1 tg1 transfer gate clock 1 (for blue) output drain voltage v od sel 300/1200 dpi select input 1-300 shift register clock 1 (for 300 dpi) 2-300 shift register clock 2 (for 300 dpi) 1-300 shift register clock 1 (for 300 dpi) 2-300 shift register clock 2 (for 300 dpi) last stage shift register clock 1 1l 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 gnd ground v out 3 output signal 3 (red) 10680 10680 10680 red green blue 1 1 1 tg3 transfer gate clock 3 (for red) tg2 transfer gate clock 2 (for green) shift register clock 2 (for 1200 dpi) 2-1200 shift register clock 1 (for 1200 dpi) 1-1200 gnd ground reset gate clock rb last stage shift register clock 2 2l reset feed-through level level clamp clock clb no connection nc caution connect the no connection pins (nc) to gnd.
data sheet s16039ej2v0ds 4 pd8891 photocell structure diagram 1200 dpi sensor 300 dpi sensor 5.25 m 2.75 m m 2.5 channel stopper aluminium shield 8.0 m 8.0 m m 2.5 channel stopper aluminium shield photocell array structure diagram 1 (line spacing) blue photocell array 1200 dpi sensor 300 dpi sensor blue photocell array green photocell array green photocell array 5.25 m 8 lines (42 m) 2 lines (10.5 m) 5.25 m 5.25 m 5.25 m 5.25 m 5.25 m red photocell array red photocell array 8 lines (42 m) 10 lines (52.5 m) 42 m 5.25 m 10 lines (52.5 m) 2 lines (10.5 m) 5.25 m 5.25 m 5.25 m blue photocell array 10.5 m green photocell array 10.5 m red photocell array 10.5 m 4 lines (42 m) 4 lines (42 m)
data sheet s16039ej2v0ds 5 pd8891 photocell array structure diagram 2 (the relation of the photocell array) 1-45 47-145 147 149 151 153 155 157 ? 2-46 48-146 148 150 152 154 156 158 ? 1-12 12 pixels 300 dpi 1200 dpi 13-37 25 pixels 2 pixels 2670 pixels 38, 39 2709 40 2710, 2711 2 pixels 46 pixels 100 pixels 8 pixels 10680 pixels 8 pixels dummy optical black invalid photocell valid photocell invalid photocell ? 10832 10834 10836-10842 10831 10833 10835-10841
data sheet s16039ej2v0ds 6 pd8891 absolute maximum ratings (t a = + + + + 25 c) parameter symbol ratings unit output drain voltage v od ? 0.3 to + 15 v shift register clock voltage v 1-300 , v 1-1200 , v 1l , ? 0.3 to + 8v v 2-300 , v 2-1200 , v 2l reset gate clock voltage v rb ? 0.3 to + 8v reset feed-through level clamp clock voltage v clb ? 0.3 to + 8v 300/1200 dpi select signal voltage v sel ? 0.3 to + 8v transfer gate clock voltage v tg1 to v tg3 ? 0.3 to + 8v operating ambient temperature note t a 0 to + 60 c storage temperature t stg ? 40 to + 70 c note use at the condition without dew condensation. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = + + + + 25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v 1-300h , v 1-1200h , v 1lh , 4.75 5.0 5.25 v v 2-300h , v 2-1200h , v 2lh shift register clock low level v 1-300l , v 1-1200l , v 1ll , ? 0.3 0 + 0.25 v v 2-300l , v 2-1200l , v 2ll reset gate clock high level v rbh 4.5 5.0 5.5 v reset gate clock low level v rbl ? 0.3 0 + 0.5 v reset feed-through level clamp clock high level v clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v clbl ? 0.3 0 + 0.5 v 300/1200 dpi select signal high level v selh 4.5 5.0 5.5 v 300/1200 dpi select signal low level v sell ? 0.3 0 + 0.5 v transfer gate clock high level v tg1h to v tg3h 4.75 v 1-300h , v 1-1200h note v 1-300h , v 1-1200h note v transfer gate clock low level v tg1l to v tg3l ? 0.3 0 + 0.15 v data rate f rb ? 2.0 5.0 mhz note when transfer gate clock high level (v tg1h to v tg3h ) is higher than shift register clock high level (v 1-300h , v 1-1200h ), image lag can increase.
data sheet s16039ej2v0ds 7 pd8891 electrical characteristics t a = + 25 c, v od = 12 v, data rate (f rb ) = 2 mhz, storage time = 11.0 ms, input signal clock = 5 v p-p , light source : 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm) + ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 300 dpi 2.5 2.7 ? v 1200 dpi 2.0 2.4 ? v saturation exposure red ser 300 dpi ? 0.167 ? lx?s 1200 dpi ? 0.445 ? lx?s green seg 300 dpi ? 0.176 ? lx?s 1200 dpi ? 0.470 ? lx?s blue seb 300 dpi ? 0.274 ? lx?s 1200 dpi ? 0.732 ? lx?s photo response non-uniformity prnu v out = 1.0 v ? 620% average dark signal ads light shielding 300 dpi ? 0.4 4.0 mv light shielding 1200 dpi ? 0.2 2.0 mv dark signal non-uniformity dsnu light shielding 300 dpi ? 4.0 12.0 mv light shielding 1200 dpi ? 2.0 6.0 mv power consumption p w ? 300 480 mw output impedance z o ? 0.4 1.0 k ? response red r r 300 dpi 11.32 16.17 21.02 v/lx?s 1200 dpi 3.77 5.39 7.01 v/lx?s green r g 300 dpi 10.73 15.33 19.93 v/lx?s 1200 dpi 3.58 5.11 6.64 v/lx?s blue r b 300 dpi 6.89 9.84 12.79 v/lx?s 1200 dpi 2.30 3.28 4.26 v/lx?s offset level note 1 v os 4.5 6.0 7.5 v image lag il v out = 1.0 v ? 3.0 7.0 % output fall delay time note 2 t d v out = 1.0 v ? 25 ? ns total transfer efficiency tte v out = 1.0 v, data rate = 5 mhz 92 98 ? % register imbalance ri v out = 1.0 v (1200 dpi) ? 1.0 4.0 % response peak red ? 630 ? nm green ? 540 ? nm blue ? 460 ? nm dynamic range dr1 v sat /dsnu 300 dpi ? 675 ? times v sat /dsnu 1200 dpi ? 1200 ? times dr2 v sat / cds 300 dpi ? 2700 ? times v sat / cds 1200 dpi ? 2400 ? times reset feed-through noise note 1 rftn light shielding ? 2000 ? 500 + 1000 mv random noise (cds) cds light shielding ? 1.0 ? mv notes 1. refer to timing chart 2 ? ? ? ? 1 to 2 ? ? ? ? 8 . 2. when the fall time of 1l or 2l (t1?, t2?) is the typ. value (refer to timing chart 2 ? ? ? ? 1 to 2 ? ? ? ? 8 ).
data sheet s16039ej2v0ds 8 pd8891 input pin capacitance (t a = + + + + 25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c 1-300 1-300 13 ? 250 ? pf 15 ? 250 ? pf c 1-1200 1-1200 8 ? 850 ? pf shift register clock pin capacitance 2 c 2-300 2-300 14 ? 300 ? pf 16 ? 300 ? pf c 2-1200 2-1200 7 ? 850 ? pf last stage sift reset gate clock pin capacitance 1 c 1l 1l 17 ? 15 ? pf last stage sift reset gate clock pin capacitance 2 c 2l 2l 3 ? 15 ? pf reset gate clock pin capacitance c rb rb 4 ? 15 ? pf reset feed-through level clamp clock pin capacitance c clb clb 5 ? 15 ? pf 300/1200 dpi select signal pin capacitance c sel sel 19 ? 15 ? pf transfer gate clock pin capacitance c tg tg1 12 ? 200 ? pf tg2 10 ? 200 ? pf tg3 9 ? 200 ? pf 300/600/1200 mode mode description sel 300 dpi data 1-300, 2-300 1200 dpi data 1-1200, 2-1200 1 300 dpi only high use clocked flush note 2 clocked 2 600 dpi only note 1 low flush note 2 clocked use 1 line clocked 3 1200 dpi only low flush note 2 clocked use clocked notes 1. for 600 dpi mode, the reset pulse is extended to allow second line?s charge to dump immediately to dc level. 2. flush means that data is continuously sunk via reset gate.
data sheet s16039ej2v0ds 9 pd8891 timing chart 1 ? ? ? ? 1 (1200 dpi, for each color) 1 2 3 4 5 6 45 46 47 146 147 154 155 10834 10835 10842 10843 v out 1 to v out 3 rb clb (bit clamp mode) clb (line clamp mode) optical black (100 pixels) 1l 2l 1-1200, 2-1200, tg1 to tg3 invalid photocell (8 pixels) valid photocell (10680 pixels) invalid photocell (8 pixels) note note note set the rb pulse and clb pulse (bit clamp mode) to high level during the tg1 to tg3 pulse. and set the rb pulse to high level while the clb pulse is low level at line clamp mode. remark inverse pulse of the tg1 to tg3 can be used as clb at line clamp mode.
data sheet s16039ej2v0ds 10 pd8891 timing chart 1 ? ? ? ? 2 (600 dpi, even pixel, for each color) 2 4 44 46 48 50 144 146 148 154 156 158 10832 10834 10836 10842 optical black (50 pixels) invalid photocell (4 pixels) valid photocell (5340 pixels) invalid photocell (4 pixels) note note v out 1 to v out 3 rb clb (bit clamp mode) clb (line clamp mode) 1l 2l 1-1200, 2-1200, tg1 to tg3 note set the rb pulse and clb pulse (bit clamp mode) to high level during the tg1 to tg3 pulse. and set the rb pulse to high level while the clb pulse is low level at line clamp mode. remark inverse pulse of the tg1 to tg3 can be used as clb at line clamp mode.
data sheet s16039ej2v0ds 11 pd8891 timing chart 1 ? ? ? ? 3 (600 dpi, odd pixel, for each color) 1 3 43 45 47 49 143 145 147 153 155 157 10831 10833 10835 10841 optical black (50 pixels) invalid photocell (4 pixels) valid photocell (5340 pixels) invalid photocell (4 pixels) note note v out 1 to v out 3 rb clb (bit clamp mode) clb (line clamp mode) 1l 2l 1-1200, 2-1200, tg1 to tg3 note set the rb pulse and clb pulse (bit clamp mode) to high level during the tg1 to tg3 pulse. and set the rb pulse to high level while the clb pulse is low level at line clamp mode. remark inverse pulse of the tg1 to tg3 can be used as clb at line clamp mode.
data sheet s16039ej2v0ds 12 pd8891 timing chart 1 ? ? ? ? 4 (300 dpi, for each color) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 36 37 38 39 40 41 2708 2709 2710 2711 2712 optical black (25 pixels) invalid photocell (2 pixels) valid photocell (2670 pixels) invalid photocell (2 pixel) note note v out 1 to v out 3 rb clb (bit clamp mode) clb (line clamp mode) 1l 2l 1-300, 2-300, tg1 to tg3 note set the rb pulse and clb pulse (bit clamp mode) to high level during the tg1 to tg3 pulse. and set the rb pulse to high level while the clb pulse is low level at line clamp mode. remark inverse pulse of the tg1 to tg3 can be used as clb at line clamp mode.
data sheet s16039ej2v0ds 13 pd8891 timing chart 2 ? ? ? ? 1 (1200 dpi, bit clamp mode, for each color) v out clb rb 2-1200 1-1200 90% 10% 90% 10% 90% 10% rftn rftn ? + v os t2 t1 t4 t6 t3 t5 t d 10% 90% 10% t10 t11 t8 t9 t7 2l 1l 90% 10% 90% 10% t2 ? t1 ? t4 t6 t3 t5 t d t10 t11 t8 t9 t7 symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 50 ? ns t4 50 150 ? ns t5, t6 0 5 ? ns t7 ? 5 note + 25 ? ns t8 20 50 ? ns t9, t10 0 5 ? ns t11 5 25 ? ns note min. of t7 shows that the rb and clb overlap each other. clb rb 90% 90% t7
data sheet s16039ej2v0ds 14 pd8891 timing chart 2 ? ? ? ? 2 (1200 dpi, line clamp mode, for each color) ? h ? v out clb rb 2-1200 1-1200 90% 10% 90% 10% 90% 10% v os t2 t1 t4 t6 t3 t5 t d 10% 2l 1l 90% 10% 90% 10% t2 ? t1 ? t4 t6 t3 t5 t d rftn ? + rftn symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 50 ? ns t4 50 150 ? ns t5, t6 0 5 ? ns
data sheet s16039ej2v0ds 15 pd8891 timing chart 2 ? ? ? ? 3 (600 dpi, even pixel, bit clamp mode, for each color) v out clb 90% 10% 90% 10% v os t2 t4 t6 t3 ? t3 ? t10 t8 t11 t7 t9 rb 2-1200 1-1200 90% 10% 90% 10% t5 10% t d + rftn ? 90% 10% 90% 10% t2 ? 2l 1l t1 t1 ? rftn symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3? 50 100 ? ns t4 50 370 ? ns t5, t6 0 5 ? ns t7 ? 5 note + 25 ? ns t8 100 200 ? ns t9, t10 0 5 ? ns t11 5 100 ? ns note min. of t7 shows that the rb and clb overlap each other. clb rb 90% 90% t7
data sheet s16039ej2v0ds 16 pd8891 timing chart 2 ? ? ? ? 4 (600 dpi, even pixel, line clamp mode, for each color) v out clb 90% 10% 90% 10% v os t2 t4 t6 t3 ? t3 ? rb 2-1200 1-1200 90% 10% t5 10% t d + rftn ? 90% 10% 90% 10% t2 ? 2l 1l t1 t1 ? rftn ? h ? symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3? 50 100 ? ns t4 50 370 ? ns t5, t6 0 5 ? ns
data sheet s16039ej2v0ds 17 pd8891 timing chart 2 ? ? ? ? 5 (600 dpi, odd pixel, bit clamp mode, for each color) v out clb 90% 10% 90% 10% v os t2 t4 t6 t3 ? t3 ? t10 t8 t11 t7 t9 rb 2-1200 1-1200 90% 10% 90% 10% t5 10% t d + rftn ? 90% 10% 90% 10% t2 ? 2l 1l t1 t1 ? rftn symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3? 50 100 ? ns t4 50 370 ? ns t5, t6 0 5 ? ns t7 ? 5 note + 25 ? ns t8 100 200 ? ns t9, t10 0 5 ? ns t11 5 100 ? ns note min. of t7 shows that the rb and clb overlap each other. clb rb 90% 90% t7
data sheet s16039ej2v0ds 18 pd8891 timing chart 2 ? ? ? ? 6 (600 dpi, odd pixel, line clamp mode, for each color) v out clb 90% 10% 90% 10% v os t2 t4 t6 t3 ? t3 ? rb 2-1200 1-1200 90% 10% t5 10% t d + rftn ? 90% 10% 90% 10% t2 ? 2l 1l t1 t1 ? rftn ? h ? symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3? 50 100 ? ns t4 50 370 ? ns t5, t6 0 5 ? ns
data sheet s16039ej2v0ds 19 pd8891 timing chart 2 ? ? ? ? 7 (300 dpi, bit clamp mode, for each color) v out clb 90% 10% 90% 10% v os t1 t4 t6 t3 t10 t8 t11 t7 t9 rb 2-300 1-300 90% 10% 90% 10% t5 10% t d + rftn ? t2 90% 10% 90% 10% t1 ? 2l 1l t2 ? rftn symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 50 ? ns t4 50 150 ? ns t5, t6 0 5 ? ns t7 ? 5 note + 25 ? ns t8 20 50 ? ns t9, t10 0 5 ? ns t11 5 25 ? ns note min. of t7 shows that the rb and clb overlap each other. clb rb 90% 90% t7
data sheet s16039ej2v0ds 20 pd8891 timing chart 2 ? ? ? ? 8 (300 dpi, line clamp mode, for each color) clb 90% 10% 90% 10% t1 t4 t6 t3 rb 2-300 1-300 90% 10% t5 t2 90% 10% 90% 10% t1 ? 2l 1l t2 ? ? h ? v out v os 10% t d + rftn ? rftn symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 50 ? ns t4 50 150 ? ns t5, t6 0 5 ? ns
data sheet s16039ej2v0ds 21 pd8891 tg1 to tg3, 1, 2 timing chart rb clb (bit clamp mode) tg1 to tg3 clb (line clamp mode) 1-1200 1-300, 2-1200 2-300, 10% 90% 90% 90% 90% 90% 90% 10% t12 t13 t17 t7 t19 t9 t20 t10 t23 t21 t22 t11 note 1 note 2 t18 t16 t15 t14 symbol min. typ. max. unit t7 ? 5 note 3 + 25 ? ns t9, t10 0 5 ? ns t11 5 25 ? ns t12 5000 10000 50000 ns t13, t14 0 50 ? ns t15, t16 900 1000 ? ns t17, t18 200 400 ? ns t19 t12 t12 50000 ns t20, t21 0 50 ? ns t22, t23 0 350 ? ns notes 1. set the rb pulse and clb pulse (bit clamp mode) to high level during this period. 2. set the rb pulse to high level during this period. 3. min. of t7 shows that the rb and clb overlap each other. clb rb 90% 90% t7 remark inverse pulse of the tg1 to tg3 can be used as clb.
data sheet s16039ej2v0ds 22 pd8891 1-300, 2-300 cross points 1-300 2-300 1.0 v to 4.0 v 1.0 v to 4.0 v 1-1200, 2-1200 cross points 1-1200 2-1200 1.0 v to 4.0 v 1.0 v to 4.0 v 1-300, 1-1200, 2l cross points 1-1200 1-300, 2l 2.0 v or more 0.5 v or more 2-300, 1-1200, 1l cross points 2-1200 2-300, 1l 2.0 v or more 0.5 v or more remark adjust cross points ( 1-300, 2-300), ( 1-1200, 2-1200), ( 1-300, 1-1200, 2l) and ( 2-300, 1- 1200, 1l) with input resistance of each pin.
data sheet s16039ej2v0ds 23 pd8891 definitions of characteristic items 1. saturation voltage : v sat output signal voltage at which the response linearity is lost. 2. saturation exposure : se product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j x x : maximum of ? x j ? x ? x valid pixels j = 1 valid pixels x j 100 ? ? x register dark dc level v out x ? 4. average dark signal : ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. ads (mv) = d j : dark signal of valid pixel number j valid pixels j = 1 valid pixels d j
data sheet s16039ej2v0ds 24 pd8891 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j ? ads ? j = 1 to valid pixels ads dsnu register dark dc level v out 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lx?s). note that the response varies with a light source (spectral characteristic). 8. image lag : il the rate between the last output voltage and the next one after read out the data of a line. v out tg light v out on off v 1 il (%) = v 1 v out 100
data sheet s16039ej2v0ds 25 pd8891 9. register imbalance : ri (1200 dpi) the rate of the difference between the averages of the output voltage of odd and even bits, against the average output voltage of all the valid pixels. ri (%) = 2 n j = 1 j = 1 n 2 (v 2j ? 1 ? v 2j ) 1 n n v j 100 n v j : number of valid pixels : output voltage of each pixel 10. random noise (cds) : cds random noise cds is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). cds is calculated by the following procedure. 1. one valid photocell in one reading is fixed as measurement point. 2. the output level is measured during the reset feed-through period which is averaged over 100 ns to get ?vd i ?. 3. the output level is measured during the video output time averaged over 100 ns to get ?vo i ?. 4. the correlated double sampling output is defined by vcds i = vd i ? vo i 5. repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. calculate the standard deviation cds using the following formula equation. cds (mv) = , v = i = 1 100 (vcds i ? v) 2 i = 1 100 vcds i 100 100 1 reset feed-through video output
data sheet s16039ej2v0ds 26 pd8891 standard characteristic curves (reference value) dark output temperature characteristic storage time output voltage characteristic (t a = +25 c) operating ambient temperature t a ( c) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 400 500 600 700 800 100 80 60 40 20 0 b b g r g response ratio (%) wavelength (nm) total spectral response characteristics (without infrared cut filter and heat absorbing filter ) (t a = +25 c)
data sheet s16039ej2v0ds 27 pd8891 application circuit example + pd8891 +5 v +12 v +5 v 0.1 f 47 f/25 v b2 b1 b3 47 ? 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 150 ? 150 ? 150 ? 4.7 ? 4.7 ? 4.7 ? 4.7 ? 10 ? nc v out 1 2-1200 1-1200 tg1 v out 2 v out 3 gnd rb 1l 2-300 1-300 2l 2-300 1-300 tg3 v od sel tg 1l 2-300 1-300 sel gnd clb 2-1200 1-1200 rb 2l clb nc tg2 47 ? + 0.1 f 10 f/16 v + 0.1 f 10 f/16 v 4.7 ? 10 ? 10 ? 4.7 ? caution connect the no connection pins (nc) to gnd. remarks 1. the inverters shown in the above application circuit example are the 74hc04 (data rate < 2 mhz) or the 74ac04 (2 data rate < 5 mhz). 2. b1 to b3 in the application circuit example are shown in the figure blow. 47 f/25 v b1 to b3 equivalent circuit + 12 v 100 ? 100 ? ccd v out 2sc945 2 k ? +
data sheet s16039ej2v0ds 28 pd8891 package drawing 44.0 0.3 37.5 1st valid pixel 0.5 0.3 1 9.25 0.3 2.0 0.25 0.05 10.16 0.2 0.46 0.1 2.54 0.25 1.02 0.15 (5.42) 4.21 0.5 4.39 0.4 12 11 2.62 0.2 3 (1.72) 2 name dimensions refractive index plastic cap 42.9 8.35 0.7 1.5 1 1st valid pixel the center of the pin1 2 the surface of the ccd chip the top of the cap 3 the bottom of the package the surface of the ccd chip 22c-1ccd-pkg11-1 (unit : mm) 1 22 10.16 + 0.7 ? 0.2 ccd linear image sensor 22-pin plastic dip (10.16 mm (400) ) pd8891cy
data sheet s16039ej2v0ds 29 pd8891 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8891cy : ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) process conditions partial heating method pin temperature : 300 c or below, heat time : 3 seconds or less (per pin) cautions 1. during assembly care should be taken to prevent solder or flux from contacting the plastic cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. so the method cannot be guaranteed.
data sheet s16039ej2v0ds 30 pd8891 notes on handling the packages cleaning the plastic cap dust and dirt protecting mounting of the package operate and storage environments ethyl alcohol methyl alcohol isopropyl alcohol n-methyl pyrrolidone etoh meoh ipa nmp the optical characteristics of the ccd will be degraded if the cap is scratched during cleaning. don ? t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. should dirt stick to a plastic cap surface, blow it off with an air blower. for dirt stuck through electricity ionized air is recommended. and if the plastic cap surface is grease stained, clean with our recommended solvents. care should be taken when cleaning the surface to prevent scratches. we recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. excessive pressure should not be applied to the cap during cleaning. if the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. the following are the recommended solvents for cleaning the ccd plastic cap. use of solvents other than these could result in optical or physical degradation in the plastic cap. please consult your sales office when considering an alternative solvent. the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with plastic cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) 1 2 electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m ? . 4 3 recommended solvents solvents symbol
data sheet s16039ej2v0ds 31 pd8891 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd8891 the information in this document is current as of march, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec e lectronics c orporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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